Forwarding a packet in a switch or a router involves executing look-ups in a series of tables to obtain an output port for the packet and instructions to re-write packet headers. Typically, high-speed switching application specific integrated circuits (ASICs) use a pipelined architecture with dedicated on-chip resources for these lookup tables. However, such designs are rigid. For example, when the tables are unused, the on-chip resources cannot be used for other purposes.
Network processors allow flexible and efficient use of resources but operate relatively slowly compared to an ASIC. Some attempts have been made to bridge the gap between rigid ASICs and relatively slower network processors. For example, some architectures introduce “programmability” in the tables whereby any new protocol header can be parsed and looked up flexibly, and arbitrary actions can be performed on the packet at the same speed as an ASIC and with similar flexibility as network processors.